Despite the complexity and high costs of chip design, it is essential to offer students the opportunity to gain practical experience early on in order to combat the shortage of skilled workers in this industry. The community initiative "Tiny Tapeout" provides bachelor students with a cost-effective opportunity to bring their own designs onto a chip. The Computer Engineering group, led by Prof. Dr. Matthias Jung, has successfully developed a chip for the second time.

DRAM's power consumption is a major concern in todays systems. Therefore, we are really happy that the committee of HiPEAC’s RAPIDO workshop acknowledged this with the best paper award for our brand new Power Simulator DRAMpower 5. The paper will be published soon in the ACM library. Also checkout the github project for the newest updates!

As off-chip memory accesses nowadays dominate the overall power consumption of many compute platforms, accurate DRAM power simulation models are an important tool for system designers. Unfortunately, existing open-source models only support older generations of DRAM standards, while current system designs mainly rely on the newest generation including DDR5, LPDDR5 or HBM3.