Publications

• Novel System Simulation Framework for HBM2 FPGA Platforms. Hernandez, Hector Gerardo Muñoz; Iskandar, Veronia; Steiner, Lukas; Holzinger, Philipp; Jung, Matthias; Goehringer, Diana; Huebner, Michael; Wehn, Norbert; Reichenbach, Marc. Springer, 2024.
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  @inproceedings{hernandez2024novel, author = {Hernandez, Hector Gerardo Muñoz and Iskandar, Veronia and Steiner, Lukas and Holzinger, Philipp and Jung, Matthias and Goehringer, Diana and Huebner, Michael and Wehn, Norbert and Reichenbach, Marc}, keywords = {sys:relevantfor:ce_uniwue}, publisher = {Springer}, title = {Novel System Simulation Framework for HBM2 FPGA Platforms}, year = 2024 }
• The New Costs of Physical Memory Fragmentation. Halbuer, Alexander; Ostapyshyn, Illia; Steiner, Lukas; Wrenger, Lars; Jung, Matthias; Dietrich, Christian; Lohmann, Daniel. In Proceedings of the 2nd Workshop on Disruptive Memory Systems, of DIMES ’24, pp. 33–40. Association for Computing Machinery, Austin, TX, USA, 2024.
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  @inproceedings{10.1145/3698783.3699378, abstract = {External fragmentation is becoming a serious problem again after paging temporarily solved it with its one-size-fits-all 4 KiB approach. The increasing adoption of mixed base, huge, and giant page sizes, DRAM energy-saving techniques, and memory disaggregation, necessitates a memory management system capable of handling larger entities in the range of multiple megabytes up to several gigabytes.A case study in Linux reveals that the operating system reasonably minimizes fragmentation up to huge page size, but falls short when it comes to larger granularities. Therefore, it requires much effort to entirely free a memory block for powering down or returning it to the memory provider; in some cases, this may be entirely impossible due to immovable kernel memory.Additionally, our analysis highlights that the page cache is responsible for a large share of memory usage, as it keeps all cached pages until memory pressure rises. This behavior originates from the outdated assumption that utilizing memory comes at no cost and, therefore, requires further investigation.}, address = {New York, NY, USA}, author = {Halbuer, Alexander and Ostapyshyn, Illia and Steiner, Lukas and Wrenger, Lars and Jung, Matthias and Dietrich, Christian and Lohmann, Daniel}, booktitle = {Proceedings of the 2nd Workshop on Disruptive Memory Systems}, keywords = {myown}, pages = {33–40}, publisher = {Association for Computing Machinery}, series = {DIMES '24}, title = {The New Costs of Physical Memory Fragmentation}, year = 2024 }
• QCEDA: Using Quantum Computers for EDA. Jung, Matthias; Krumke, Sven O.; Schroth, Christof; Lobe, Elisabeth; Mauerer, Wolfgang. In International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS). Springer, 2024.
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  @inproceedings{jung2024qceda, author = {Jung, Matthias and Krumke, Sven O. and Schroth, Christof and Lobe, Elisabeth and Mauerer, Wolfgang}, booktitle = {International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)}, keywords = {myown}, publisher = {Springer}, title = {QCEDA: Using Quantum Computers for EDA}, year = 2024 }
• How Far Is the Nanocellulose Chip and Its Production in Reach? A Literature Survey. Bencurova, Elena; Chinazzo, André; Kar, Bipasa; Jung, Matthias; Dandekar, Thomas. In Nanomaterials, 14(18). 2024.
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  @article{benchi_24, abstract = {The slowdown of Moore’s Law necessitates an exploration of novel computing methodologies, new materials, and advantages in chip design. Thus, carbon-based materials have promise for more energy-efficient computing systems in the future. Moreover, sustainability emerges as a new concern for the semiconductor industry. The production and recycling processes associated with current chips present huge environmental challenges. Electronic waste is a major problem, and sustainable solutions in computing must be found. In this review, we examine an alternative chip design based on nanocellulose, which also features semiconductor properties and transistors. Our review highlights that nanocellulose (NC) is a versatile material and a high-potential composite, as it can be fabricated to gain suitable electronic and semiconducting properties. NC provides ideal support for ink-printed transistors and electronics, including green paper electronics. Here, we summarise various processing procedures for nanocellulose and describe the structure of exclusively nanocellulose-based transistors. Furthermore, we survey the recent scientific efforts in organic chip design and show how fully automated production of such a full NC chip could be achieved, including a Process Design Kit (PDK), expected variation models, and a standard cell library at the logic-gate level, where multiple transistors are connected to perform basic logic operations—for instance, the NOT-AND (NAND) gate. Taking all these attractive nanocellulose features into account, we envision how chips based on nanocellulose can be fabricated using Electronic Design Automation (EDA) tool chains.}, author = {Bencurova, Elena and Chinazzo, André and Kar, Bipasa and Jung, Matthias and Dandekar, Thomas}, journal = {Nanomaterials}, keywords = {myown}, number = 18, title = {How Far Is the Nanocellulose Chip and Its Production in Reach? A Literature Survey}, volume = 14, year = 2024 }
• Challenges for Quantum Software Engineering: An Industrial Application Scenario Perspective. Carbonelli, Cecilia; Felderer, Michael; Jung, Matthias; Lobe, Elisabeth; Lochau, Malte; Luber, Sebastian; Mauerer, Wolfgang; Ramler, Rudolf; Schaefer, Ina; Schroth, Christoph. In Quantum Software: Aspects of Theory and System Design, I. Exman, R. Pérez-Castillo, M. Piattini, M. Felderer (eds.), pp. 311–335. Springer Nature Switzerland, Cham, 2024.
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  @inbook{Carbonelli2024, abstract = {Quantum software is becoming a key enabler for applying quantum computing to industrial use cases. This poses challenges to quantum software engineering in providing efficient and effective means to develop such software. Eventually, this must be reliably achieved in time, on budget, and in quality, using sound and well-principled engineering approaches. Given that quantum computers are based on fundamentally different principles than classical machines, this raises the question if, how, and to what extent established techniques for systematically engineering software need to be adapted. In this chapter, we analyze three paradigmatic application scenarios for quantum software engineering from an industrial perspective. The respective use cases center around (1) optimization and quantum cloud services, (2) quantum simulation, and (3) embedded quantum computing. Our aim is to provide a concise overview of the current and future applications of quantum computing in diverse industrial settings. We derive presumed challenges for quantum software engineering and thus provide research directions for this emerging field.}, address = {Cham}, author = {Carbonelli, Cecilia and Felderer, Michael and Jung, Matthias and Lobe, Elisabeth and Lochau, Malte and Luber, Sebastian and Mauerer, Wolfgang and Ramler, Rudolf and Schaefer, Ina and Schroth, Christoph}, booktitle = {Quantum Software: Aspects of Theory and System Design}, editor = {Exman, Iaakov and P{\'e}rez-Castillo, Ricardo and Piattini, Mario and Felderer, Michael}, keywords = {myown}, pages = {311–335}, publisher = {Springer Nature Switzerland}, title = {Challenges for Quantum Software Engineering: An Industrial Application Scenario Perspective}, year = 2024 }
• DARC- Amateurfunklehrgang Klasse N. Amberg, Matthias; Bartels, Henrik; Behrens, Jan; Berka, Helmut; Dahlke, Mathias; Danowski, Michael; Deharde, Sabrina; Finkenzeller, Klaus; Funke, Michael; Groni, Michael; Hartje, Michael; Hillmer, Christian; Jerke, Ronny; Jung, Matthias; Kless, Erich; Krause, Karlheinz; Kregel, Stephan; Krüger, Andreas; Lowack, Michael; Mittendorf, Daniel; Rode, Harald; Schmid, Florian; Schumacher, Alexander; Schwan, Marco; Schwarz, Hans; Swierczek, Björn; Thielmann, Aaron; Weber, Carmen; Weiler, Lars; Wiedemann, Severin. First , M. Jung; B. Swierczek (eds.). DARC Verlag, 2024.
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  @book{2024amateurfunklehrgang, abstract = {Willkommen in der faszinierenden Welt des Amateurfunks! Der Amateurfunkdienst bietet nicht nur die Möglichkeit zur persönlichen Wissenserweiterung durch Experimente und kontinuierliche Weiterbildung, sondern erlaubt auch, einen Beitrag zur globalen Verständigung zu leisten. Zudem kann der Amateurfunkdienst bei Hilfsaktionen in Not- und Katastrophenfällen unterstützen. Es ist wichtig zu betonen, dass der Amateurfunkdienst auf gleicher Ebene mit anderen Funkdiensten, wie zum Beispiel Mobilfunk, Rundfunk und Flugfunk, steht. Als Teilnehmer am Amateurfunkdienst besitzt man das Recht, eigene Sende- und Empfangsanlagen zu entwickeln und zu betreiben. Der Amateurfunk eröffnet die Möglichkeit, mit einer Vielzahl von Übertragungsverfahren zu experimentieren – von der klassischen Kurzwelle über Satellitenfunk bis hin zum Internet der Dinge, einschließlich neuer Verfahren mithilfe von künstlicher Intelligenz. Für die Teilnahme am Amateurfunkdienst ist ein Amateurfunkzeugnis erforderlich, das durch eine erfolgreiche Prüfung bei der Bundesnetzagentur erlangt wird. In Deutschland gliedert sich der Amateurfunk in drei Klassen: die Klasse N für Neueinsteiger, die erweiterte Klasse E und die Klasse A mit höchster Leistung auf allen zugeteilten Frequenzen. Diese Buchreihe dient der Vorbereitung auf die Prüfungen für die verschiedenen Amateurfunkklassen. Es ist zu beachten, dass die Prüflinge unterschiedliche Vorkenntnisse mitbringen. Für manche kann es ratsam sein, die Prüfungen für die verschiedenen Klassen in aufeinanderfolgender Reihenfolge abzulegen, während andere den direkten Weg zur Klasse A wählen. Einige finden im Selbststudium mit einem Buch oder einem Online-Kurs ausreichend Unterstützung, während andere einen Präsenzkurs oder einen persönlichen Ansprechpartner bevorzugen. Diese Buchreihe sowie die dazu gehörige Online-Plattform sind darauf ausgerichtet, all diesen unterschiedlichen Lernstile gerecht zu werden.}, author = {Amberg, Matthias and Bartels, Henrik and Behrens, Jan and Berka, Helmut and Dahlke, Mathias and Danowski, Michael and Deharde, Sabrina and Finkenzeller, Klaus and Funke, Michael and Groni, Michael and Hartje, Michael and Hillmer, Christian and Jerke, Ronny and Jung, Matthias and Kless, Erich and Krause, Karlheinz and Kregel, Stephan and Krüger, Andreas and Lowack, Michael and Mittendorf, Daniel and Rode, Harald and Schmid, Florian and Schumacher, Alexander and Schwan, Marco and Schwarz, Hans and Swierczek, Björn and Thielmann, Aaron and Weber, Carmen and Weiler, Lars and Wiedemann, Severin}, edition = {First}, editor = {Jung, Matthias and Swierczek, Björn}, keywords = {from:myzinsky}, month = {06}, publisher = {DARC Verlag}, title = {DARC- Amateurfunklehrgang Klasse N}, year = 2024 }
• PIMSys: A Virtual Prototype for Processing in Memory. Christ, Derek; Steiner, Lukas; Wehn, Norbert; Jung, Matthias. In 10th International Symposium on Memory Systems (MEMSYS 2024). 2024.
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  @inproceedings{christ2024pimsys, author = {Christ, Derek and Steiner, Lukas and Wehn, Norbert and Jung, Matthias}, booktitle = {10th International Symposium on Memory Systems (MEMSYS 2024)}, keywords = {from:myzinsky}, title = {PIMSys: A Virtual Prototype for Processing in Memory}, year = 2024 }

• Automatic DRAM Subsystem Configuration with irace. Steiner, Lukas; Delazeri, Gustavo; Prando Da Silva, Iron; Jung, Matthias; Wehn, Norbert. In Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO). International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on, 2023.
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  @inproceedings{steiner2023automatic, author = {Steiner, Lukas and Delazeri, Gustavo and Prando Da Silva, Iron and Jung, Matthias and Wehn, Norbert}, booktitle = {Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)}, keywords = {myown}, organization = {International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on}, title = {Automatic DRAM Subsystem Configuration with irace}, year = 2023 }
• Neues Ausbildungsmaterial für alle Klassen. Jung, Matthias; Swierczek, Björn. In Amateurfunk-Tagung München. DARC e.V., Distrikt Oberbayern, 2023.
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  @inproceedings{junswi_23, author = {Jung, Matthias and Swierczek, Björn}, booktitle = {Amateurfunk-Tagung München}, keywords = {myown}, publisher = {DARC e.V., Distrikt Oberbayern}, title = {Neues Ausbildungsmaterial für alle Klassen}, year = 2023 }
• A Precise Measurement Platform for LPDDR4 Memories. Feldmann, Johannes; Steiner, Lukas; Christ, Derek; Psota, Thomas; Jung, Matthias; Wehn, Norbert. In ACM/IEEE International Symposium on Memory Systems (MEMSYS 2023). 2023.
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  @inproceedings{feldmann2023precise, author = {Feldmann, Johannes and Steiner, Lukas and Christ, Derek and Psota, Thomas and Jung, Matthias and Wehn, Norbert}, booktitle = {ACM/IEEE International Symposium on Memory Systems (MEMSYS 2023)}, keywords = {myown}, title = {A Precise Measurement Platform for LPDDR4 Memories}, year = 2023 }

• A Framework for Formal Verification of DRAM Controllers. Steiner, Lukas; Sudarshan, Chirag; Jung, Matthias; Stoffel, Dominik; Wehn, Norbert. In ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022). 2022.
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  @inproceedings{stesud_22, author = {Steiner, Lukas and Sudarshan, Chirag and Jung, Matthias and Stoffel, Dominik and Wehn, Norbert}, booktitle = {ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022)}, keywords = {myown}, title = {A Framework for Formal Verification of DRAM Controllers}, year = 2022 }
• Unveiling the Real Performance of LPDDR5 Memories. Steiner, Lukas; Jung, Matthias; Huonker, Michael; Wehn, Norbert. In ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022). 2022.
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  @inproceedings{stejun_22, author = {Steiner, Lukas and Jung, Matthias and Huonker, Michael and Wehn, Norbert}, booktitle = {ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022)}, keywords = {myown}, title = {Unveiling the Real Performance of LPDDR5 Memories}, year = 2022 }
• DRAMSys4.0: An Open-Source Simulation Framework for In-Depth DRAM Analyses. Steiner, Lukas; Jung, Matthias; Prado, Felipe; Bykov, Kyrill; Wehn, Norbert. In Springer, International Journal of Parallel Programming (IJPP). 2022.
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  @article{stejun_22, author = {Steiner, Lukas and Jung, Matthias and Prado, Felipe and Bykov, Kyrill and Wehn, Norbert}, journal = {Springer, International Journal of Parallel Programming (IJPP)}, keywords = {myown}, title = {{DRAMS}ys4.0: {A}n {O}pen-{S}ource {S}imulation {F}ramework for {I}n-{D}epth {DRAM} {A}nalyses}, year = 2022 }
• Amateurfunkprüfung: Zwischenstand neuer Fragenkatalog. Jung, Matthias; Swierczek, Björn. In Weinheimer UKW-Tagung. 2022.
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  @inproceedings{junswi_22, author = {Jung, Matthias and Swierczek, Björn}, booktitle = {Weinheimer UKW-Tagung}, keywords = {myown}, title = {Amateurfunkprüfung: Zwischenstand neuer Fragenkatalog}, year = 2022 }
• A Weighted Current Summation based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. Sudarshan, Chirag; Soliman, Taha; Lappas, Jan; Weis, Christian; Sadi, Mohammad H.; Jung, Matthias; Guntoro, Andre; Wehn, Norbert. In Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS). 2022.
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  @article{sudsol_22, author = {Sudarshan, Chirag and Soliman, Taha and Lappas, Jan and Weis, Christian and Sadi, Mohammad H. and Jung, Matthias and Guntoro, Andre and Wehn, Norbert}, journal = {Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)}, keywords = {myown}, title = {{A} {W}eighted {C}urrent {S}ummation based {M}ixed {S}ignal {DRAM}-{PIM} {A}rchitecture for {D}eep {N}eural {N}etwork {I}nference}, year = 2022 }
• Split’n’Cover: ISO26262 Hardware Safety Analysis with SystemC. Uecker, Denis; Jung, Matthias. In Springer LNCS International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS). 2022.
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  @inproceedings{uecker2022splitncover, author = {Uecker, Denis and Jung, Matthias}, booktitle = {Springer LNCS International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)}, keywords = {myown}, title = {Split'n'Cover: ISO26262 Hardware Safety Analysis with SystemC}, year = 2022 }

• A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation. Sudarshan, Chirag; Steiner, Lukas; Jung, Matthias; Lappas, Jan; Weis, Christian; Wehn, Norbert. In IEEE Transactions on Circuits and Systems II: Express Briefs. 2021.
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  @article{sudste_21, author = {Sudarshan, Chirag and Steiner, Lukas and Jung, Matthias and Lappas, Jan and Weis, Christian and Wehn, Norbert}, journal = {IEEE Transactions on Circuits and Systems II: Express Briefs}, keywords = {myown}, title = {{A} {N}ovel {DRAM} {A}rchitecture for {I}mproved {B}andwidth {U}tilization and {L}atency {R}eduction {U}sing {D}ual-{P}age {O}peration}, year = 2021 }
• SEC-Learn: Sensor Edge Cloud for Federated Learning. Aichroth, Patrick; Antes, Christoph; Gembatzka, Pierre; Graf, Holger; Johnson, David; Jung, Matthias; Kämpfe, Thomas; Kleinberger, Thomas; Köllmer, Thomas; Kuhn, Thomas; Kutter, Christoph; Krüger, Jens; Loroch, Dominik; Lukashevich, Hanna; Zhang, Lei; Laleni, Nellie; Leugering, Johannes; Fernandez, Rodrigo; Mateu, Loreto; Mojumder, Shaown; Prautsch, Benjamin; Roscher, Karsten; Schneickert, Sören; Vanselow, Frank; Wallbott, Paul; Walter, Oliver; Weber, Nico. In Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXI). 2021.
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  @inproceedings{aicant_21, author = {Aichroth, Patrick and Antes, Christoph and Gembatzka, Pierre and Graf, Holger and Johnson, David and Jung, Matthias and Kämpfe, Thomas and Kleinberger, Thomas and Köllmer, Thomas and Kuhn, Thomas and Kutter, Christoph and Krüger, Jens and Loroch, Dominik and Lukashevich, Hanna and Zhang, Lei and Laleni, Nellie and Leugering, Johannes and Fernandez, Rodrigo and Mateu, Loreto and Mojumder, Shaown and Prautsch, Benjamin and Roscher, Karsten and Schneickert, Sören and Vanselow, Frank and Wallbott, Paul and Walter, Oliver and Weber, Nico}, booktitle = {Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXI)}, keywords = {myown}, month = {07}, title = {{SEC}-{L}earn: {S}ensor {E}dge {C}loud for {F}ederated {L}earning}, year = 2021 }
• A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. Sudarshan, Chirag; Soliman, Taha; de la Parra, C.; Weis, Christian; Ecco, Leonardo; Jung, Matthias; Wehn, Norbert; Guntoro, Andre. In 26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021). 2021.
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  @inproceedings{sudsol_21, author = {Sudarshan, Chirag and Soliman, Taha and de la Parra, C. and Weis, Christian and Ecco, Leonardo and Jung, Matthias and Wehn, Norbert and Guntoro, Andre}, booktitle = {26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021)}, keywords = {myown}, month = {01}, title = {{A} {N}ovel {DRAM}-{B}ased {P}rocess-in-{M}emory {A}rchitecture and its {I}mplementation for {CNN}s}, year = 2021 }
• An LPDDR4 Safety Model for Automotive Applications. Steiner, Lukas; Kraft, Kira; Uecker, Denis; Jung, Matthias; Huonker, Michael; Wehn, Norbert. In ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021). 2021.
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  @inproceedings{stekra_21, author = {Steiner, Lukas and Kraft, Kira and Uecker, Denis and Jung, Matthias and Huonker, Michael and Wehn, Norbert}, booktitle = {ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021)}, keywords = {myown}, month = 10, title = {{A}n {LPDDR}4 {S}afety {M}odel for {A}utomotive {A}pplications}, year = 2021 }
• Exploration of DDR5 with the Open Source Simulator DRAMSys. Steiner, Lukas; Jung, Matthias; Wehn, Norbert. In IEEE/VDE Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen MBMV. 2021.
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  @inproceedings{stejun_21, author = {Steiner, Lukas and Jung, Matthias and Wehn, Norbert}, booktitle = {IEEE/VDE Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen MBMV}, keywords = {myown}, title = {{E}xploration of {DDR}5 with the {O}pen {S}ource {S}imulator {DRAMS}ys}, year = 2021 }
• Online Working Set Change Detection with Constant Complexity. Vasan, Gokul; Zulian, Éder F.; Weis, Christian; Jung, Matthias; Wehn, Norbert. In ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021). 2021.
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  @inproceedings{vaszul_21, author = {Vasan, Gokul and Zulian, Éder F. and Weis, Christian and Jung, Matthias and Wehn, Norbert}, booktitle = {ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021)}, keywords = {myown}, month = 10, title = {{O}nline {W}orking {S}et {C}hange {D}etection with {C}onstant {C}omplexity}, year = 2021 }
• The Dynamic Random Access Memory Challenge in Embedded Computing Systems (Book Chapter in: A Journey of Embedded and Cyber-Physical Systems: Essays Dedicated to Peter Marwedel on the Occasion of His 70th {B}irthday). Jung, Matthias; Weis, Christian; Wehn, Norbert. Springer International Publishing, 2021.
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  @book{junwei_21, author = {Jung, Matthias and Weis, Christian and Wehn, Norbert}, keywords = {myown}, publisher = {Springer International Publishing}, title = {{T}he {D}ynamic {R}andom {A}ccess {M}emory {C}hallenge in {E}mbedded {C}omputing {S}ystems ({B}ook {C}hapter in: {A} {J}ourney of {E}mbedded and {C}yber-{P}hysical {S}ystems: {E}ssays {D}edicated to {P}eter {M}arwedel on the {O}ccasion of {H}is 70th {B}irthday)}, year = 2021 }

• System Simulation with PULP Virtual Platform and SystemC. Zulian, Éder F.; Haugou, Germain; Weis, Christian; Jung, Matthias; Wehn, Norbert. In International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO). 2020.
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  @inproceedings{zulhau_20, author = {Zulian, Éder F. and Haugou, Germain and Weis, Christian and Jung, Matthias and Wehn, Norbert}, booktitle = {International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)}, keywords = {myown}, month = {01}, title = {{S}ystem {S}imulation with {PULP} {V}irtual {P}latform and {S}ystem{C}}, year = 2020 }
• Fast and Accurate DRAM Simulation: Can we Further Accelerate it?. Jung, Matthias; Feldmann, Johannes; Kraft, Kira; Steiner, Lukas; Wehn, Norbert. In 2020 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 364–369. 2020.
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  @inproceedings{junfel_20, author = {Jung, Matthias and Feldmann, Johannes and Kraft, Kira and Steiner, Lukas and Wehn, Norbert}, booktitle = {2020 Design, Automation Test in Europe Conference Exhibition (DATE)}, keywords = {myown}, pages = {364-369}, title = {{F}ast and {A}ccurate {DRAM} {S}imulation: {C}an we {F}urther {A}ccelerate it?}, year = 2020 }
• The gem5 Simulator: Version 20.0+. Lowe-Power, Jason; Ahmad, Abdul Mutaal; Akram, Ayaz; Alian, Mohammad; Amslinger, Rico; Andreozzi, Matteo; Armejach, Adrià; Asmussen, Nils; Bharadwaj, Srikant; Black, Gabe; Bloom, Gedare; Bruce, Bobby R.; Carvalho, Daniel Rodrigues; Castrillon, Jeronimo; Chen, Lizhong; Derumigny, Nicolas; Diestelhorst, Stephan; Elsasser, Wendy; Fariborz, Marjan; Farmahini-Farahani, Amin; Fotouhi, Pouya; Gambord, Ryan; Gandhi, Jayneel; Gope, Dibakar; Grass, Thomas; Hanindhito, Bagus; Hansson, Andreas; Haria, Swapnil; Harris, Austin; Hayes, Timothy; Herrera, Adrian; Horsnell, Matthew; Jafri, Syed Ali Raza; Jagtap, Radhika; Jang, Hanhwi; Jeyapaul, Reiley; Jones, Timothy M.; Jung, Matthias; Kannoth, Subash; Khaleghzadeh, Hamidreza; Kodama, Yuetsu; Krishna, Tushar; Marinelli, Tommaso; Menard, Christian; Mondelli, Andrea; Mück, Tiago; Naji, Omar; Nathella, Krishnendra; Nguyen, Hoa; Nikoleris, Nikos; Olson, Lena E.; Orr, Marc; Pham, Binh; Prieto, Pablo; Reddy, Trivikram; Roelke, Alec; Samani, Mahyar; Sandberg, Andreas; Setoain, Javier; Shingarov, Boris; Sinclair, Matthew D.; Ta, Tuan; Thakur, Rahul; Travaglini, Giacomo; Upton, Michael; Vaish, Nilay; Vougioukas, Ilias; Wang, Zhengrong; Wehn, Norbert; Weis, Christian; Wood, David A.; Yoon, Hongil; Zulian, Éder F. 2020.
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  @article{lowgem520, author = {Lowe-Power, Jason and Ahmad, Abdul Mutaal and Akram, Ayaz and Alian, Mohammad and Amslinger, Rico and Andreozzi, Matteo and Armejach, Adrià and Asmussen, Nils and Bharadwaj, Srikant and Black, Gabe and Bloom, Gedare and Bruce, Bobby R. and Carvalho, Daniel Rodrigues and Castrillon, Jeronimo and Chen, Lizhong and Derumigny, Nicolas and Diestelhorst, Stephan and Elsasser, Wendy and Fariborz, Marjan and Farmahini-Farahani, Amin and Fotouhi, Pouya and Gambord, Ryan and Gandhi, Jayneel and Gope, Dibakar and Grass, Thomas and Hanindhito, Bagus and Hansson, Andreas and Haria, Swapnil and Harris, Austin and Hayes, Timothy and Herrera, Adrian and Horsnell, Matthew and Jafri, Syed Ali Raza and Jagtap, Radhika and Jang, Hanhwi and Jeyapaul, Reiley and Jones, Timothy M. and Jung, Matthias and Kannoth, Subash and Khaleghzadeh, Hamidreza and Kodama, Yuetsu and Krishna, Tushar and Marinelli, Tommaso and Menard, Christian and Mondelli, Andrea and Mück, Tiago and Naji, Omar and Nathella, Krishnendra and Nguyen, Hoa and Nikoleris, Nikos and Olson, Lena E. and Orr, Marc and Pham, Binh and Prieto, Pablo and Reddy, Trivikram and Roelke, Alec and Samani, Mahyar and Sandberg, Andreas and Setoain, Javier and Shingarov, Boris and Sinclair, Matthew D. and Ta, Tuan and Thakur, Rahul and Travaglini, Giacomo and Upton, Michael and Vaish, Nilay and Vougioukas, Ilias and Wang, Zhengrong and Wehn, Norbert and Weis, Christian and Wood, David A. and Yoon, Hongil and Zulian, Éder F.}, keywords = {myown}, title = {{T}he gem5 {S}imulator: {V}ersion 20.0+}, year = 2020 }
• eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. Stathis, Dimitrios; Sudarshan, Chirag; Yang, Yu; Jung, Matthias; Weis, Christian; Hemani, Ahmed; Lansner, Anders; Wehn, Norbert. In Journal of Signal Processing Systems. 2020.
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  @article{stasud_20, abstract = {The Artificial Neural Networks (ANNs), like CNN/DNN and LSTM, are not biologically plausible. Despite their initial success, they cannot attain the cognitive capabilities enabled by the dynamic hierarchical associative memory systems of biological brains. The biologically plausible spiking brain models, e.g., cortex, basal ganglia, and amygdala, have a greater potential to achieve biological brain like cognitive capabilities. Bayesian Confidence Propagation Neural Network (BCPNN) is a biologically plausible spiking model of the cortex. A human-scale model of BCPNN in real-time requires 162 TFlop/s, 50 TBs of synaptic weight storage to be accessed with a bandwidth of 200 TBs. The spiking bandwidth is relatively modest at 250 GBs/s. A hand-optimized implementation of rodent scale BCPNN has been done on Tesla K80 GPUs require 3 kWs, we extrapolate from that a human scale network will require 3 MWs. These power numbers rule out such implementations for field deployment as cognition engines in embedded systems.}, author = {Stathis, Dimitrios and Sudarshan, Chirag and Yang, Yu and Jung, Matthias and Weis, Christian and Hemani, Ahmed and Lansner, Anders and Wehn, Norbert}, journal = {Journal of Signal Processing Systems}, keywords = {myown}, month = {07}, title = {e{B}rain{II}: a 3 k{W} {R}ealtime {C}ustom 3{D} {DRAM} {I}ntegrated {ASIC} {I}mplementation of a {B}iologically {P}lausible {M}odel of a {H}uman {S}cale {C}ortex}, year = 2020 }
• Moderne Speicherarchitekturen für leistungsfähige Infotainmentsysteme und autonomes Fahren. Jung, Matthias; Huonker, Michael; Kalmar, Ralf; Wehn, Norbert. In ATZelektronik, 15(11), pp. 16–21. 2020.
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  @article{junhuo_20, author = {Jung, Matthias and Huonker, Michael and Kalmar, Ralf and Wehn, Norbert}, journal = {ATZelektronik}, keywords = {myown}, month = 11, number = 11, pages = {16-21}, title = {{M}oderne {S}peicherarchitekturen f{\"u}r leistungsf{\"a}hige {I}nfotainmentsysteme und autonomes {F}ahren}, volume = 15, year = 2020 }
• An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices. Mathew, Deepak M.; Prado, Felipe S.; Zulian, Éder. F.; Weis, Christian; Ghaffar, Muhammad Mohsin; Jung, Matthias; Wehn, Norbert. In International Symposium on Memory Systems (MEMSYS 2020). ACM/IEEE, 2020.
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  @inproceedings{matpra_20, author = {Mathew, Deepak M. and Prado, Felipe S. and Zulian, Éder. F. and Weis, Christian and Ghaffar, Muhammad Mohsin and Jung, Matthias and Wehn, Norbert}, booktitle = {International Symposium on Memory Systems (MEMSYS 2020)}, keywords = {myown}, month = 10, publisher = {ACM/IEEE}, title = {{A}n {E}nergy {E}fficient 3{D}-{H}eterogeneous {M}ain {M}emory {A}rchitecture for {M}obile {D}evices}, year = 2020 }
• DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator. Steiner, Lukas; Jung, Matthias; Prado, Felipe S.; Bykov, Kyrill; Wehn, Norbert. In International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS). Springer, 2020.
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  @inproceedings{stejun_20, author = {Steiner, Lukas and Jung, Matthias and Prado, Felipe S. and Bykov, Kyrill and Wehn, Norbert}, booktitle = {International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)}, keywords = {myown}, month = {07}, publisher = {Springer}, title = {{DRAMS}ys4.0: {A} {F}ast and {C}ycle-{A}ccurate {S}ystem{C}/{TLM}-{B}ased {DRAM} {S}imulator}, year = 2020 }
• Efficient Generation of Application Specific Memory Controllers. Natale, Marco V.; Jung, Matthias; Kraft, Kira; Lauer, Frederik; Feldmann, Johannes; Sudarshan, Chirag; Weis, Christian; Krumke, Sven O.; Wehn, Norbert. In International Symposium on Memory Systems (MEMSYS 2020). ACM/IEEE, 2020.
  • [ BibTeX ]
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  @inproceedings{natjun_20, author = {Natale, Marco V. and Jung, Matthias and Kraft, Kira and Lauer, Frederik and Feldmann, Johannes and Sudarshan, Chirag and Weis, Christian and Krumke, Sven O. and Wehn, Norbert}, booktitle = {International Symposium on Memory Systems (MEMSYS 2020)}, keywords = {myown}, month = 10, publisher = {ACM/IEEE}, title = {{E}fficient {G}eneration of {A}pplication {S}pecific {M}emory {C}ontrollers}, year = 2020 }
• A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions. Ghaffar, Muhammad Mohsin; Sudarshan, Chirag; Weis, Christian; Jung, Matthias; Wehn, Norbert. In International Symposium on Memory Systems (MEMSYS 2020). ACM/IEEE, 2020.
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  @inproceedings{ghasud_20, author = {Ghaffar, Muhammad Mohsin and Sudarshan, Chirag and Weis, Christian and Jung, Matthias and Wehn, Norbert}, booktitle = {International Symposium on Memory Systems (MEMSYS 2020)}, keywords = {myown}, month = 10, publisher = {ACM/IEEE}, title = {A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions}, year = 2020 }

• RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM. Mathew, Deepak; Chinazzo, André Lucas; Weis, Christian; Jung, Matthias; Giraud, Bastien; Vivet, Pascal; Levisse, Alexandre; Wehn, Norbert. In 2019 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). 2019.
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  @inproceedings{matchi_19, author = {Mathew, Deepak and Chinazzo, Andr\'e Lucas and Weis, Christian and Jung, Matthias and Giraud, Bastien and Vivet, Pascal and Levisse, Alexandre and Wehn, Norbert}, booktitle = {2019 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)}, keywords = {myown}, month = {07}, title = {{RRAMS}pec: {A} {D}esign {S}pace {E}xploration {F}ramework for {H}igh {D}ensity {R}esistive {RAM}}, year = 2019 }
• 3D Stacked DRAM Memories (Book chapter in the Handbook of 3D {I}ntegration). Weis, Christian; Jung, Matthias; Wehn, Norbert. Vol. 4. Wiley-VCH, 2019.
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  @book{weijun_16, author = {Weis, Christian and Jung, Matthias and Wehn, Norbert}, keywords = {myown}, publisher = {Wiley-VCH}, title = {3{D} {S}tacked {DRAM} {M}emories ({B}ook chapter in the {H}andbook of 3{D} {I}ntegration)}, volume = 4, year = 2019 }
• Fast Validation of DRAM Protocols with Timed Petri Nets. Jung, Matthias; Kraft, Kira; Soliman, Taha; Sudarshan, Chirag; Weis, Christian; Wehn, Norbert. In Proceedings of the International Symposium on Memory Systems, of MEMSYS ’19, pp. 133–147. ACM, Washington, District of Columbia, 2019.
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  @inproceedings{junkra_19, address = {New York, NY, USA}, author = {Jung, Matthias and Kraft, Kira and Soliman, Taha and Sudarshan, Chirag and Weis, Christian and Wehn, Norbert}, booktitle = {Proceedings of the International Symposium on Memory Systems}, keywords = {validation}, pages = {133–147}, publisher = {ACM}, series = {MEMSYS '19}, title = {{F}ast {V}alidation of {DRAM} {P}rotocols with {T}imed {P}etri {N}ets}, year = 2019 }
• Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling. Jahic, Jasmin; Kumar, Varun; Jung, Matthias; Wirrer, Gerhard; Wehn, Norbert; Kuhn, Thomas. In Proceedings of the 48th International Conference on Parallel Processing: Workshops, of ICPP 2019. Association for Computing Machinery, Kyoto, Japan, 2019.
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  @inproceedings{jahkum_19, address = {New York, NY, USA}, author = {Jahic, Jasmin and Kumar, Varun and Jung, Matthias and Wirrer, Gerhard and Wehn, Norbert and Kuhn, Thomas}, booktitle = {Proceedings of the 48th International Conference on Parallel Processing: Workshops}, keywords = {embedded}, publisher = {Association for Computing Machinery}, series = {ICPP 2019}, title = {{R}apid {I}dentification of {S}hared {M}emory in {M}ultithreaded {E}mbedded {S}ystems with {S}tatic {S}cheduling}, year = 2019 }
• Speculative Temporal Decoupling Using fork(). Jung, Matthias; Schnicke, Frank; Damm, Markus; Kuhn, Thomas; Wehn, Norbert. In IEEE Conference on Design, Automation and Test in Europe (DATE), pp. 1721–1726. 2019.
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  @inproceedings{junsch_19, author = {Jung, Matthias and Schnicke, Frank and Damm, Markus and Kuhn, Thomas and Wehn, Norbert}, booktitle = {IEEE Conference on Design, Automation and Test in Europe (DATE)}, keywords = {myown}, month = {03}, pages = {1721-1726}, title = {{S}peculative {T}emporal {D}ecoupling {U}sing fork()}, year = 2019 }
• A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing. Sudarshan, Chirag; Lappas, Jan; Weis, Christian; Mathew, Deepak M.; Jung, Matthias; Wehn, Norbert. In Embedded Computer Systems: Architectures, Modeling, and Simulation, D. N. Pnevmatikatos, M. Pelcat, M. Jung (eds.), pp. 429–441. Springer International Publishing, Cham, 2019.
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  @inproceedings{sudlap_19a, abstract = {Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting heterogeneous and approximate computing techniques. One of the recent evolution in this context is transprecision computing paradigm. The idea of the transprecision computing is to consume adequate amount of energy for each operation by performing dynamic precision reduction. The impact of the memory subsystem plays a crucial role in such systems. Hence, the energy efficiency of a transprecision system can be further optimized by tailoring the memory subsystem to the transprecision computing. In this work, we present a lean, low power, low latency memory controller that is appropriate for transprecision methodology. The memory controller consumes an average power of 129.33 mW at a frequency of 500 MHz and has a total area of 4.71 mm2 for UMC 65 nm process.}, address = {Cham}, author = {Sudarshan, Chirag and Lappas, Jan and Weis, Christian and Mathew, Deepak M. and Jung, Matthias and Wehn, Norbert}, booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation}, editor = {Pnevmatikatos, Dionisios N. and Pelcat, Maxime and Jung, Matthias}, keywords = {myown}, pages = {429–441}, publisher = {Springer International Publishing}, title = {{A} {L}ean, {L}ow {P}ower, {L}ow {L}atency {DRAM} {M}emory {C}ontroller for {T}ransprecision {C}omputing}, year = 2019 }
• NNDRAM: A Deep In-DRAM Computing Architecture for Neural Network Processing. Sudarshan, Chirag; Lappas, Jan; Ghaffar, Muhammad Mohsin; Rybalkin, Vladimir; Weis, Christian; Jung, Matthias; Wehn, Norbert. In IEEE International Symposium on Circuits and Systems (ISCAS). 2019.
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  • [ DOI ]
  @inproceedings{sudlap_19, author = {Sudarshan, Chirag and Lappas, Jan and Ghaffar, Muhammad Mohsin and Rybalkin, Vladimir and Weis, Christian and Jung, Matthias and Wehn, Norbert}, booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)}, keywords = {myown}, month = {05}, title = {{NNDRAM}: {A} {D}eep {I}n-{DRAM} {C}omputing {A}rchitecture for {N}eural {N}etwork {P}rocessing}, year = 2019 }

• Driving into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving. Jung, Matthias; McKee, Sally A.; Sudarshan, Chirag; Dropmann, Christoph; Weis, Christian; Wehn, Norbert. In Proceedings of the International Symposium on Memory Systems, of MEMSYS ’18, pp. 377–386. ACM, Alexandria, Virginia, 2018.
  • [ BibTeX ]
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  @inproceedings{junmck_18, address = {New York, NY, USA}, author = {Jung, Matthias and McKee, Sally A. and Sudarshan, Chirag and Dropmann, Christoph and Weis, Christian and Wehn, Norbert}, booktitle = {Proceedings of the International Symposium on Memory Systems}, keywords = {DRAM,}, pages = {377–386}, publisher = {ACM}, series = {MEMSYS '18}, title = {{D}riving into the {M}emory {W}all: {T}he {R}ole of {M}emory for {A}dvanced {D}river {A}ssistance {S}ystems and {A}utonomous {D}riving}, year = 2018 }
• A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs. Brugger, Christian; Grigorovici, Valentin; Jung, Matthias; De Schryver, Christian; Weis, Christian; Wehn, Norbert; Zweig, Katharina Anna. In IEEE Design & Test, 35(1), pp. 7–15. 2018.
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  @article{brugri_17, author = {Brugger, Christian and Grigorovici, Valentin and Jung, Matthias and De Schryver, Christian and Weis, Christian and Wehn, Norbert and Zweig, Katharina Anna}, journal = {IEEE Design \& Test}, keywords = {graphics;storage}, month = {02}, number = 1, pages = {7-15}, title = {{A} {M}emory {C}entric {A}rchitecture of the {L}ink {A}ssessment {A}lgorithm in {L}arge {G}raphs}, volume = 35, year = 2018 }
• BOSMI: A Framework for Non-intrusive Monitoring and Testing of Embedded Multithreaded Software on the Logical Level. Jahić, Jasmin; Kuhn, Thomas; Jung, Matthias; Wehn, Norbert. In Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, of SAMOS ’18, pp. 131–138. ACM, Pythagorion, Greece, 2018.
  • [ BibTeX ]
  • [ URL ]
  • [ DOI ]
  @inproceedings{jahkuh_18, address = {New York, NY, USA}, author = {Jahić, Jasmin and Kuhn, Thomas and Jung, Matthias and Wehn, Norbert}, booktitle = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation}, keywords = {execution}, pages = {131–138}, publisher = {ACM}, series = {SAMOS '18}, title = {{BOSMI}: {A} {F}ramework for {N}on-intrusive {M}onitoring and {T}esting of {E}mbedded {M}ultithreaded {S}oftware on the {L}ogical {L}evel}, year = 2018 }
• Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property. Kraft, Kira; Jung, Matthias; Sudarshan, Chiarg; Mathew, Deepak M.; Weis, Christian; Wehn, Norbert. In IEEE Conference Design, Automation and Test in Europe (DATE). 2018.
  • [ BibTeX ]
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  @inproceedings{krajun_18, author = {Kraft, Kira and Jung, Matthias and Sudarshan, Chiarg and Mathew, Deepak M. and Weis, Christian and Wehn, Norbert}, booktitle = {IEEE Conference Design, Automation and Test in Europe (DATE)}, keywords = {myown}, month = {03}, title = {{I}mproving the {E}rror {B}ehavior of {DRAM} by {E}xploiting its {Z}-{C}hannel {P}roperty}, year = 2018 }
• A Framework for Non-Intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration. Jahić, Jasmin; Jung, Matthias; Kuhn, Thomas; Kestel, Claus; Wehn, Norbert. In The 18th International Conference on Runtime Verification (RV 2018). 2018.
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  @inproceedings{jahjun_18, author = {Jahić, Jasmin and Jung, Matthias and Kuhn, Thomas and Kestel, Claus and Wehn, Norbert}, booktitle = {The 18th International Conference on Runtime Verification (RV 2018)}, keywords = {myown}, month = 11, title = {{A} {F}ramework for {N}on-{I}ntrusive {T}race-driven {S}imulation of {M}anycore {A}rchitectures with {D}ynamic {T}racing {C}onfiguration}, year = 2018 }
• Enabling Continuous Software Engineering for Embedded Systems Architectures with Virtual Prototypes. Antonino, Pablo Oliveira; Jung, Matthias; Morgenstern, Andreas; Faßnacht, Florian; Bauer, Thomas; Bachorek, Adam; Kuhn, Thomas; Nakagawa, Elisa Yumi. In Software Architecture, C. E. Cuesta, D. Garlan, J. Pérez (eds.), pp. 115–130. Springer International Publishing, Cham, 2018.
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  @inproceedings{olijun_18, abstract = {Continuous software engineering aims at orchestrating engineering knowledge from various disciplines in order to deal with the rapid changes within the ecosystems of which software-based systems are part of. The literature claims that one means to ensure these prompt responses is to incorporate virtual prototypes of the system as early as possible in the development process, such that requirements and architecture decisions are verified early and continuously by means of simulations. Despite the maturity of practices for designing and assessing architectures, as well as for virtual prototyping, it is still not clear how to jointly consider the practices from these disciplines within development processes, in order to address the dynamics imposed by continuous software engineering. In this regard, we discuss in this paper how to orchestrate architecture drivers and design specification techniques with virtual prototypes, to address the demands of continuous software engineering in development processes. Our proposals are based on experiences from research and industry projects in various domains such as automotive, agriculture, construction, and medical devices.}, address = {Cham}, author = {Antonino, Pablo Oliveira and Jung, Matthias and Morgenstern, Andreas and Fa{\ss}nacht, Florian and Bauer, Thomas and Bachorek, Adam and Kuhn, Thomas and Nakagawa, Elisa Yumi}, booktitle = {Software Architecture}, editor = {Cuesta, Carlos E. and Garlan, David and P{\'e}rez, Jennifer}, keywords = {myown}, pages = {115–130}, publisher = {Springer International Publishing}, title = {{E}nabling {C}ontinuous {S}oftware {E}ngineering for {E}mbedded {S}ystems {A}rchitectures with {V}irtual {P}rototypes}, year = 2018 }
• Driving Against the Memory Wall: The Role of Memory for Autonomous Driving. Jung, Matthias; Wehn, Norbert. In Workshop on New Platforms for Future Cars: Current and Emerging Trends at IEEE Conference Design, Automation and Test in Europe (DATE). 2018.
  • [ BibTeX ]
  • [ URL ]
  @conference{junweh_18, author = {Jung, Matthias and Wehn, Norbert}, booktitle = {Workshop on New Platforms for Future Cars: Current and Emerging Trends at IEEE Conference Design, Automation and Test in Europe (DATE)}, keywords = {myown}, month = {03}, title = {{D}riving {A}gainst the {M}emory {W}all: {T}he {R}ole of {M}emory for {A}utonomous {D}riving}, year = 2018 }
• Efficient Coding Scheme for DDR4 Memory Subsystems. Kraft, Kira; Mathew, Deepak M.; Sudarshan, Chirag; Jung, Matthias; Weis, Christian; Wehn, Norbert; Longnos, Florian. In ACM International Symposium on Memory Systems (MEMSYS 2018). 2018.
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  • [ DOI ]
  @inproceedings{kramat_18, author = {Kraft, Kira and Mathew, Deepak M. and Sudarshan, Chirag and Jung, Matthias and Weis, Christian and Wehn, Norbert and Longnos, Florian}, booktitle = {ACM International Symposium on Memory Systems (MEMSYS 2018)}, keywords = {myown}, month = 10, title = {{E}fficient {C}oding {S}cheme for {DDR}4 {M}emory {S}ubsystems}, year = 2018 }
• The Role of Memories in Transprecision Computing. Weis, Christian; Jung, Matthias; Zulian, Éder F.; Sudarshan, Chirag; Mathew, Deepak; Wehn, Norbert. In IEEE International Symposium on Circuits and Systems (ISCAS). 2018.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{weijun_18, author = {Weis, Christian and Jung, Matthias and Zulian, Éder F. and Sudarshan, Chirag and Mathew, Deepak and Wehn, Norbert}, booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)}, keywords = {myown}, month = {05}, title = {{T}he {R}ole of {M}emories in {T}ransprecision {C}omputing}, year = 2018 }
• A Model-Based Safety Analysis of Dependencies Across Abstraction Layers. Dropmann, Christoph; Thaden, Eike; Trapp, Mario; Uecker, Denis; Amarnath, Rakshith; da Silva, Leandro Avila; Munk, Peter; Schweizer, Markus; Jung, Matthias; Adler, Rasmus. In Computer Safety, Reliability, and Security, B. Gallina, A. Skavhaug, F. Bitsch (eds.), pp. 73–87. Springer International Publishing, Cham, 2018.
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  @inproceedings{drotha_18, abstract = {Identifying and mitigating possible failure propagation from one safety-critical application to another through common infrastructural components is a challenging task. Examples of such dependencies across software-stack layers (e.g., between application and middleware layer) are common causes and failure propagation scenarios in which a failure of one software component propagates to another software component through shared services and/or common computational resources. To account for this, safety standards demand freedom from interference in order to control failure propagation between mixed-critical software components. Safety analysis is typically focused on one abstraction layer, while robustness tests try to find failure propagation paths across abstraction layers. To this end, this paper presents a model-based failure propagation analysis combining failure propagation within and across abstraction layers. A classification of dependencies in combination with fault trees is used to perform a model-based dependency analysis. In addition, a novel modeling technique for integrating failure propagation aspects resulting from shared services and resources is presented. The analysis was used to carry out an early safety assessment of a real-world automotive redundancy mechanism within an integrated architecture. The results show that the method improved reusability and modularity, and made it easier to estimate failure propagation issues, including possible violations of freedom from interference within an integrated system.}, address = {Cham}, author = {Dropmann, Christoph and Thaden, Eike and Trapp, Mario and Uecker, Denis and Amarnath, Rakshith and da Silva, Leandro Avila and Munk, Peter and Schweizer, Markus and Jung, Matthias and Adler, Rasmus}, booktitle = {Computer Safety, Reliability, and Security}, editor = {Gallina, Barbara and Skavhaug, Amund and Bitsch, Friedemann}, keywords = {myown}, pages = {73–87}, publisher = {Springer International Publishing}, title = {{A} {M}odel-{B}ased {S}afety {A}nalysis of {D}ependencies {A}cross {A}bstraction {L}ayers}, year = 2018 }
• An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs. Mathew, Deepak M.; Schultheis, Martin; Rheinländer, Carl C.; Sudarshan, Chirag; Jung, Matthias; Weis, Christian; Wehn, Norbert. In IEEE Conference Design, Automation and Test in Europe (DATE). 2018.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{matsch_18, author = {Mathew, Deepak M. and Schultheis, Martin and Rheinländer, Carl C. and Sudarshan, Chirag and Jung, Matthias and Weis, Christian and Wehn, Norbert}, booktitle = {IEEE Conference Design, Automation and Test in Europe (DATE)}, keywords = {myown}, title = {{A}n {A}nalysis on {R}etention {E}rror {B}ehavior and {P}ower {C}onsumption of {R}ecent {DDR}4 {DRAM}s}, year = 2018 }

• 3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. Liu, Pei; Hemani, Ahmed; Paul, Kolin; Weis, Christian; Jung, Matthias; Wehn, Norbert. In International Journal of Parallel Programming, pp. 1–41. 2017.
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  @article{liuhem_17, abstract = {Sequence analysis plays extremely important role in bioinformatics, and most applications of which have compute intensive kernels consuming over 70{\%} of total execution time. By exploiting the compute intensive execution stages of popular sequence analysis applications, we present and evaluate a VLSI architecture with a focus on those that target at biological sequences directly, including pairwise sequence alignment, multiple sequence alignment, database search, and short read sequence mappings. Based on coarse grained reconfigurable array we propose the use of many-core and 3D-stacked technologies to gain further improvement over memory subsystem, which gives another order of magnitude speedup from high bandwidth and low access latency. We analyze our approach in terms of its throughput and efficiency for different application mappings. Initial experimental results are evaluated from a stripped down implementation in a commodity FPGA, and then we scale the results to estimate the performance of our architecture with 9 layers of {\$}{\$}70 {\backslash}hbox {\{} mm{\}}^{\{}2{\}}{\$}{\$} 70 mm 2 stacked wafers in 45-nm process. We demonstrate numerous estimated speedups better than corresponding existed hardware accelerator platforms for at least 40 times for the entire range of applications and datasets of interest. In comparison, the alternative FPGA based accelerators deliver only improvement for single application, while GPGPUs perform not well enough on accelerating program kernel with random memory access and integer addition/comparison operations.}, author = {Liu, Pei and Hemani, Ahmed and Paul, Kolin and Weis, Christian and Jung, Matthias and Wehn, Norbert}, journal = {International Journal of Parallel Programming}, keywords = {myown}, pages = {1–41}, title = {3{D}-{S}tacked {M}any-{C}ore {A}rchitecture for {B}iological {S}equence {A}nalysis {P}roblems}, year = 2017 }
• Integrating DRAM Power-Down Modes in gem5 and Quantifying their Impact. Jagtap, Radhika; Jung, Matthias; Elsasser, Wendy; Weis, Christian; Hansson, Andreas; Wehn, Norbert. In International Symposium on Memory Systems (MEMSYS17). 2017.
  • [ BibTeX ]
  • [ DOI ]
  @conference{jagjun_17, author = {Jagtap, Radhika and Jung, Matthias and Elsasser, Wendy and Weis, Christian and Hansson, Andreas and Wehn, Norbert}, booktitle = {International Symposium on Memory Systems (MEMSYS17)}, keywords = {myown}, title = {{I}ntegrating {DRAM} {P}ower-{D}own {M}odes in gem5 and {Q}uantifying their {I}mpact}, year = 2017 }
• DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool. Weis, Christian; Mutaal, Abdul; Naji, Omar; Jung, Matthias; Hansson, Andreas; Wehn, Norbert. In International Journal of Parallel Programming, 45(6), pp. 1566–1591. 2017.
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  • [ URL ]
  • [ DOI ]
  @article{weimut_16, abstract = {In systems ranging from mobile devices to servers, DRAM has a big impact on performance and contributes a significant part of the total consumed power. The performance and power of the system depends on the architecture of the DRAM chip, the design of the memory controller and the access patterns received by the memory controller. Thus, evaluating the impact of DRAM design decisions requires a holistic approach that includes an appropriate model of the DRAM bank, a realistic controller and DRAM power model, and a representative workload, which requires a full system simulator running a complete software stack. In this paper, we introduce DRAMSpec, a high-level DRAM bank/chip modeling tool. Our contribution is to move the DRAM modeling abstraction level from the circuit level to the DRAM bank and by the integration in full system simulators we allow system or processor designers (non-DRAM experts) to tune future DRAM architectures for their target applications. We demonstrate the merits of DRAMSpec by exploring the influence of DRAM row-buffer (page) size and the number of banks on performance and power of a server application (memcached). Our new DRAM design offers a 16{\%} DRAM performance improvement and 13{\%} DRAM energy saving compared to standard comodity DDR3 devices. Additionally, we demonstrate how our tool is able to aid in evaluating novel DRAM architectures, such as the Hybrid Memory Cube (HMC), for which no DRAM datasheets are available. Finally, we highlight the DRAM technology scaling for a specific HMC architecture and we quantify the impact on latency and power.}, author = {Weis, Christian and Mutaal, Abdul and Naji, Omar and Jung, Matthias and Hansson, Andreas and Wehn, Norbert}, journal = {International Journal of Parallel Programming}, keywords = {myown}, month = 12, number = 6, pages = {1566–1591}, title = {{DRAMS}pec: {A} {H}igh-{L}evel {DRAM} {T}iming, {P}ower and {A}rea {E}xploration {T}ool}, volume = 45, year = 2017 }
• A Bank-Wise DRAM Power Model for System Simulations. Mathew, Deepak M.; Zulian, Éder F.; Kannoth, Subash; Jung, Matthias; Weis, Christian; Wehn, Norbert. In Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, of RAPIDO ’17, pp. 5:1–5:7. ACM, Stockholm, Sweden, 2017.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{matzul_17, address = {New York, NY, USA}, author = {Mathew, Deepak M. and Zulian, \'{E}der F. and Kannoth, Subash and Jung, Matthias and Weis, Christian and Wehn, Norbert}, booktitle = {Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools}, keywords = {DRAM,}, pages = {5:1–5:7}, publisher = {ACM}, series = {RAPIDO '17}, title = {{A} {B}ank-{W}ise {DRAM} {P}ower {M}odel for {S}ystem {S}imulations}, year = 2017 }
• A New State Model for DRAMs Using Petri Nets. Jung, Matthias; Kraft, Kira; Wehn, Norbert. In 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp. 221–226. 2017.
  • [ BibTeX ]
  • [ DOI ]
  @conference{junkra_17, author = {Jung, Matthias and Kraft, Kira and Wehn, Norbert}, booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)}, keywords = {memory;Standards}, month = {07}, pages = {221-226}, title = {{A} {N}ew {S}tate {M}odel for {DRAM}s {U}sing {P}etri {N}ets}, year = 2017 }
• A Platform to Analyze DDR3 DRAM’s Power and Retention Time. Jung, Matthias; Mathew, Deepak; Rheinländer, Carl; Weis, Christian; Wehn, Norbert. In IEEE Design & Test, 34(4), pp. 52–59. 2017.
  • [ BibTeX ]
  • [ DOI ]
  @article{junmat_17, author = {Jung, Matthias and Mathew, Deepak and Rheinländer, Carl and Weis, Christian and Wehn, Norbert}, journal = {IEEE Design \& Test}, keywords = {measurement;Approximate}, month = {08}, number = 4, pages = {52-59}, title = {{A} {P}latform to {A}nalyze {DDR}3 {DRAM}’s {P}ower and {R}etention {T}ime}, volume = 34, year = 2017 }
• Supervised Testing of Concurrent Software in Embedded Systems. Jahić, Jasmin; Jung, Matthias; Kuhn, Thomas; Wehn, Norbert. In 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp. 233–238. 2017.
  • [ BibTeX ]
  • [ DOI ]
  @conference{jahjun_17, author = {Jahić, Jasmin and Jung, Matthias and Kuhn, Thomas and Wehn, Norbert}, booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)}, keywords = {sets;Synchronization;Task}, month = {07}, pages = {233-238}, title = {{S}upervised {T}esting of {C}oncurrent {S}oftware in {E}mbedded {S}ystems}, year = 2017 }
• System Simulation with gem5 and SystemC: The Keystone for Full Interoperability. Menard, Christian; Jung, Matthias; Castrillon, Jeronimo; Wehn, Norbert. In 2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp. 62–69. 2017.
  • [ BibTeX ]
  • [ DOI ]
  @conference{menjun_17, author = {Menard, Christian and Jung, Matthias and Castrillon, Jeronimo and Wehn, Norbert}, booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)}, keywords = {analysis;Time-varying}, month = {07}, pages = {62-69}, title = {{S}ystem {S}imulation with gem5 and {S}ystem{C}: {T}he {K}eystone for {F}ull {I}nteroperability}, year = 2017 }
• Using Run-Time Reverse-Engineering to Optimize DRAM Refresh. Mathew, Deepak M.; Zulian, Éder F.; Jung, Matthias; Kraft, Kira; Weis, Christian; Jacob, Bruce; Wehn, Norbert. In International Symposium on Memory Systems (MEMSYS17). 2017.
  • [ BibTeX ]
  • [ DOI ]
  @conference{matzul_17a, author = {Mathew, Deepak M. and Zulian, Éder F. and Jung, Matthias and Kraft, Kira and Weis, Christian and Jacob, Bruce and Wehn, Norbert}, booktitle = {International Symposium on Memory Systems (MEMSYS17)}, keywords = {myown}, title = {{U}sing {R}un-{T}ime {R}everse-{E}ngineering to {O}ptimize {DRAM} {R}efresh}, year = 2017 }
• System-Level Modeling, Analysis and Optimization of DRAM Memories and Controller Architectures. Jung, Matthias. University of Kaiserslautern, 2017.
  • [ BibTeX ]
  • [ URL ]
  @phdthesis{jun_17, author = {Jung, Matthias}, keywords = {myown}, publisher = {University of Kaiserslautern}, school = {University of Kaiserslautern}, title = {{S}ystem-{L}evel {M}odeling, {A}nalysis and {O}ptimization of {DRAM} {M}emories and {C}ontroller {A}rchitectures}, year = 2017 }

• Software Architectures for Embedded Software Systems. Oliveira, Pablo; Morgenstern, Andreas; Jung, Matthias; Kuhn, Thomas; Wehn, Norbert. Distance and Independent Studies Center (DISC) University of Kaiserslautern, 2016.
  • [ BibTeX ]
  • [ URL ]
  @book{olimor_16, author = {Oliveira, Pablo and Morgenstern, Andreas and Jung, Matthias and Kuhn, Thomas and Wehn, Norbert}, keywords = {myown}, publisher = {Distance and Independent Studies Center (DISC) University of Kaiserslautern}, title = {{S}oftware {A}rchitectures for {E}mbedded {S}oftware {S}ystems}, year = 2016 }
• A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration. Jung, Matthias; Mathew, Deepak M.; Zulian, Éder F.; Weis, Christian; Wehn, Norbert. In International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016). 2016.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{junmat_16b, author = {Jung, Matthias and Mathew, Deepak M. and Zulian, \'Eder F. and Weis, Christian and Wehn, Norbert}, booktitle = {International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016)}, keywords = {myown}, title = {{A} {N}ew {B}ank {S}ensitive {DRAMP}ower {M}odel for {E}fficient {D}esign {S}pace {E}xploration}, year = 2016 }
• Efficient Reliability Management in SoCs - An Approximate DRAM Perspective. Jung, Matthias; Mathew, Deepak M.; Weis, Christian; Wehn, Norbert. In 21st Asia and South Pacific Design Automation Conference (ASP-DAC). 2016.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{junmat_16, author = {Jung, Matthias and Mathew, Deepak M. and Weis, Christian and Wehn, Norbert}, booktitle = {21st Asia and South Pacific Design Automation Conference (ASP-DAC)}, keywords = {myown}, title = {{E}fficient {R}eliability {M}anagement in {S}o{C}s - {A}n {A}pproximate {DRAM} {P}erspective}, year = 2016 }
• Exploring System Performance using Elastic Traces: Fast, Accurate and Portable. Jagtap, Radhika; Diestelhorst, Stephan; Hansson, Andreas; Jung, Matthias; Wehn, Norbert. In IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece. 2016.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{jagdie_16, author = {Jagtap, Radhika and Diestelhorst, Stephan and Hansson, Andreas and Jung, Matthias and Wehn, Norbert}, booktitle = {IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece}, keywords = {myown}, title = {{E}xploring {S}ystem {P}erformance using {E}lastic {T}races: {F}ast, {A}ccurate and {P}ortable}, year = 2016 }
• A cross layer approach for efficient thermal management in 3D stacked SoCs. Jung, Matthias; Weis, Christian; Wehn, Norbert. In Microelectronics Reliability, 61, pp. 43–47. 2016.
  • [ BibTeX ]
  • [ DOI ]
  @article{junwei_15a, abstract = {Abstract 3D stacking of silicon dies via Through Silicon Vias (TSVs) is an emerging technology to increase performance, energy efficiency and integration density of today's and future System-on-Chips (SoCs). Especially the stacking of Wide I/O \{DRAMs\} on top of a logic die is a very promising approach to tackle the memory wall and energy efficiency challenge. The potential of this type of stacking is currently under investigation by many research groups and companies in particular for mobile devices. There, for instance, the baseband processing and the application processor can be implemented on the same single logic die. On top of this die one or several Wide I/O \{DRAMs\} are stacked. An example of such a SoC is the \{WIOMING\} chip [15]. However, new challenges emerge, especially thermal management, which is already a very demanding challenge in current 2D SoCs. With 3D SoCs this problem exacerbates due to reliability issues such as the temperature sensitivity of DRAMs, i.e., the retention time of a \{DRAM\} cell largely decreases with increasing temperature. In this paper, we show a holistic cross layer reliability approach for efficient reliability management starting from measuring and modeling of \{DRAM\} retention errors, which finally leads to optimizations for specific applications. These optimizations exploit the data lifetime and the inherent error resilience of the application, which is for instance given in the probabilistic behavior of wireless communications.}, author = {Jung, Matthias and Weis, Christian and Wehn, Norbert}, journal = {Microelectronics Reliability}, keywords = {DRAM}, note = {ICMAT 2015 Symposium}, pages = {43 - 47}, title = {{A} cross layer approach for efficient thermal management in 3{D} stacked {S}o{C}s}, volume = 61, year = 2016 }
• ConGen: An Application Specific DRAM Memory Controller Generator. Jung, Matthias; Heinrich, Irene; Natale, Marco; Mathew, Deepak M.; Weis, Christian; Krumke, Sven; Wehn, Norbert. In Proceedings of the Second International Symposium on Memory Systems, of MEMSYS ’16, pp. 257–267. ACM, Alexandria, VA, USA, 2016.
  • [ BibTeX ]
  • [ URL ]
  • [ DOI ]
  @inproceedings{junhei_16, address = {New York, NY, USA}, author = {Jung, Matthias and Heinrich, Irene and Natale, Marco and Mathew, Deepak M. and Weis, Christian and Krumke, Sven and Wehn, Norbert}, booktitle = {Proceedings of the Second International Symposium on Memory Systems}, keywords = {Optimization}, pages = {257–267}, publisher = {ACM}, series = {MEMSYS '16}, title = {{C}on{G}en: {A}n {A}pplication {S}pecific {DRAM} {M}emory {C}ontroller {G}enerator}, year = 2016 }
• Approximate Computing with Partially Unreliable Dynamic Random Access Memory - Approximate DRAM. Jung, Matthias; Mathew, Deepak; Weis, Christian; Wehn, Norbert. In Proceedings of the 53rd Annual Design Automation Conference, of DAC ’16, pp. 100:1–100:4. ACM, Austin, Texas, 2016.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{junmat_16a, address = {New York, NY, USA}, author = {Jung, Matthias and Mathew, Deepak and Weis, Christian and Wehn, Norbert}, booktitle = {Proceedings of the 53rd Annual Design Automation Conference}, keywords = {refresh,}, pages = {100:1–100:4}, publisher = {ACM}, series = {DAC '16}, title = {{A}pproximate {C}omputing with {P}artially {U}nreliable {D}ynamic {R}andom {A}ccess {M}emory - {A}pproximate {DRAM}}, year = 2016 }
• A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D--Stacked Architecture. Liu, Pei; Hemani, Ahmed; Paul, Kolin; Weis, Christian; Jung, Matthias; Wehn, Norbert. In Journal of Signal Processing Systems, pp. 1–15. 2016.
  • [ BibTeX ]
  • [ URL ]
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  @article{liuhem_16, abstract = {Rapidly developing Next Generation Sequencing technologies produce huge amounts of short reads that consisting randomly fragmented DNA base pair strings. Assembling of those short reads poses a challenge on the mapping of reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a customized many-core hardware acceleration platform for short read mapping problems based on hash-index method. The processing core is highly customized to suite both 2-hit string matching and banded Smith-Waterman sequence alignment operations, while distributed memory interface with 3D–stacked architecture provides high bandwidth and low access latency for highly customized dataset partitioning and memory access scheduling. Conformal with original BFAST program, our design provides an amazingly 45,012 times speedup over software approach for single-end short reads and 21,102 times for paired-end short reads, while also beats similar single FPGA solution for 1466 times in case of single end reads. Optimized seed generation gives much better sensitivity while the performance boost is still impressive.}, author = {Liu, Pei and Hemani, Ahmed and Paul, Kolin and Weis, Christian and Jung, Matthias and Wehn, Norbert}, journal = {Journal of Signal Processing Systems}, keywords = {myown}, pages = {1–15}, title = {{A} {C}ustomized {M}any-{C}ore {H}ardware {A}cceleration {P}latform for {S}hort {R}ead {M}apping {P}roblems {U}sing {D}istributed {M}emory {I}nterface with 3{D}–{S}tacked {A}rchitecture}, year = 2016 }
• Reverse Engineering of DRAMs: Row Hammer with Crosshair. Jung, Matthias; Rheinländer, Carl; Weis, Christian; Wehn, Norbert. In International Symposium on Memory Systems (MEMSYS 2016). 2016.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{junrhe_16, author = {Jung, Matthias and Rheinl{\"a}nder, Carl and Weis, Christian and Wehn, Norbert}, booktitle = {International Symposium on Memory Systems (MEMSYS 2016)}, keywords = {myown}, title = {{R}everse {E}ngineering of {DRAM}s: {R}ow {H}ammer with {C}rosshair}, year = 2016 }

• Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs. Jung, Matthias; Zulian, Eder; Mathew, Deepak; Herrmann, Matthias; Brugger, Christian; Weis, Christian; Wehn, Norbert. In 1st International Symposium on Memory Systems (MEMSYS 2015). Washington, DC, USA, 2015.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{junzul_15, address = {Washington, DC, USA}, author = {Jung, Matthias and Zulian, Eder and Mathew, Deepak and Herrmann, Matthias and Brugger, Christian and Weis, Christian and Wehn, Norbert}, booktitle = {1st International Symposium on Memory Systems (MEMSYS 2015)}, keywords = {myown}, month = 10, title = {{O}mitting {R}efresh - {A} {C}ase {S}tudy for {C}ommodity and {W}ide {I}/{O} {DRAM}s}, year = 2015 }
• Reliability and Thermal Challenges in 3D Integrated Embedded Systems. Weis, Christian; Jung, Matthias; Wehn, Norbert. In 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, The Netherlands. 2015.
  • [ BibTeX ]
  • [ URL ]
  @inproceedings{weijun_15b, author = {Weis, Christian and Jung, Matthias and Wehn, Norbert}, booktitle = {1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, The Netherlands.}, keywords = {myown}, month = 10, title = {{R}eliability and {T}hermal {C}hallenges in 3{D} {I}ntegrated {E}mbedded {S}ystems}, year = 2015 }
• DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework. Jung, Matthias; Weis, Christian; Wehn, Norbert. In IPSJ Transactions on System LSI Design Methodology (T-SLDM). 2015.
  • [ BibTeX ]
  • [ DOI ]
  @article{junwei_15, author = {Jung, Matthias and Weis, Christian and Wehn, Norbert}, journal = {IPSJ Transactions on System LSI Design Methodology (T-SLDM)}, keywords = {myown}, month = {08}, title = {{DRAMS}ys: {A} flexible {DRAM} {S}ubsystem {D}esign {S}pace {E}xploration {F}ramework}, year = 2015 }
• Retention Time Measurements and Modelling of Bit Error Rates of WIDE I/O DRAM in MPSoCs. Weis, Christian; Jung, Matthias; Ehses, Peter; Santos, Cristiano; Vivet, Pascal; Goossens, Sven; Koedam, Martijn; Wehn, Norbert. In Proceedings of the IEEE Conference on Design, Automation & Test in Europe (DATE). European Design and Automation Association, 2015.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{weijun_15, author = {Weis, Christian and Jung, Matthias and Ehses, Peter and Santos, Cristiano and Vivet, Pascal and Goossens, Sven and Koedam, Martijn and Wehn, Norbert}, booktitle = {Proceedings of the IEEE Conference on Design, Automation \& Test in Europe (DATE)}, keywords = {AGWehn}, organization = {European Design and Automation Association}, title = {{R}etention {T}ime {M}easurements and {M}odelling of {B}it {E}rror {R}ates of {WIDE} {I}/{O} {DRAM} in {MPS}o{C}s}, year = 2015 }
• A High-Level DRAM Timing, Power and Area Exploration Tool. Naji, Omar; Weis, Christian; Jung, Matthias; Wehn, Norbert; Hansson, Andreas. In Embedded Computer Systems Architectures Modeling and Simulation (SAMOS). 2015.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{najwei_15, author = {Naji, Omar and Weis, Christian and Jung, Matthias and Wehn, Norbert and Hansson, Andreas}, booktitle = {Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)}, keywords = {myown}, month = {07}, title = {{A} {H}igh-{L}evel {DRAM} {T}iming, {P}ower and {A}rea {E}xploration {T}ool}, year = 2015 }
• Thermal Aspects and High-level Explorations of 3D stacked DRAMs. Weis, Christian; Jung, Matthias; Santos, Christiano; Vivet, Pascal; Naji, Omar; Hansson, Andreas; Wehn, Norbert. In IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 2015.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{weijun_15a, author = {Weis, Christian and Jung, Matthias and Santos, Christiano and Vivet, Pascal and Naji, Omar and Hansson, Andreas and Wehn, Norbert}, booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, keywords = {myown}, title = {{T}hermal {A}spects and {H}igh-level {E}xplorations of 3{D} stacked {DRAM}s}, year = 2015 }
• A Custom Computing System for Finding Similarties in Complex Networks. Brugger, Christian; Grigorovici, Valentin; Jung, Matthias; Weis, Christian; Schryver, Christian De; Zweig, Katharina A.; Wehn, Norbert. In Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 262–267. Montpellier, France, 2015.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{brugri_15, abstract = {Complex graphs are at the heart of today’s big data chal- lenges like recommendation systems, customer behavior mod- eling, or incident detection systems. One reoccurring task in these fields is the extraction of network motifs, reoccur- ring and statistically significant subgraphs. In this work we propose a precisely tailored embedded architecture for com- puting similarities based on one special network motif, the co-occurrence. It is based on efficient and scalable building blocks that exploit well-tuned algorithmic refinements and an optimized graph data representation approach. On chip, our solution features a customized cache design and a light- weight data path that allows the system to perform over 10,000 graph operations per cycle on each chip. We provide detailed area, energy, and timing results for a 28 nm ASIC process and DDR3 memory devices. Compared to an Intel cluster, our proposed solution uses 44x less memory and is 224x more energy efficient.}, address = {Montpellier, France}, author = {Brugger, Christian and Grigorovici, Valentin and Jung, Matthias and Weis, Christian and Schryver, Christian De and Zweig, Katharina A. and Wehn, Norbert}, booktitle = {Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)}, keywords = {AGWehn}, month = {07}, pages = {262–267}, title = {{A} {C}ustom {C}omputing {S}ystem for {F}inding {S}imilarties in {C}omplex {N}etworks}, year = 2015 }
• Coupling gem5 with SystemC TLM 2.0 Virtual Platforms. Jung, Matthias; Wehn, Norbert. In gem5 User Workshop, International Symposium on Computer Architecture (ISCA). Portland, OR, USA., 2015.
  • [ BibTeX ]
  • [ URL ]
  @inproceedings{junweh_15, address = {Portland, OR, USA.}, author = {Jung, Matthias and Wehn, Norbert}, booktitle = {gem5 User Workshop, International Symposium on Computer Architecture (ISCA)}, keywords = {myown}, month = {06}, title = {{C}oupling gem5 with {S}ystem{C} {TLM} 2.0 {V}irtual {P}latforms}, year = 2015 }
• Virtual Development on Mixed Abstraction Levels: an Agricultural Vehicle Case Study. Jung, Matthias; Piao, Songlin; Purusothaman, Thiyagarajan; Pan, Xiao; Kuhn, Thomas; Grimm, Christoph; Berns, Karsten; Wehn, Norbert. In Synopsys Usergroup Conference (SNUG). 2015.
  • [ BibTeX ]
  • [ URL ]
  @article{junpia_15, author = {Jung, Matthias and Piao, Songlin and Purusothaman, Thiyagarajan and Pan, Xiao and Kuhn, Thomas and Grimm, Christoph and Berns, Karsten and Wehn, Norbert}, journal = {Synopsys Usergroup Conference (SNUG)}, keywords = {myown}, month = {06}, title = {{V}irtual {D}evelopment on {M}ixed {A}bstraction {L}evels: an {A}gricultural {V}ehicle {C}ase {S}tudy}, year = 2015 }

• Energy Optimization in 3D MPSoCs with Wide-I/O DRAM Using Temperature Variation Aware Bank-Wise Refresh. Sadri, MohammadSadegh; Jung, Matthias; Weis, Christian; Wehn, Norbert; Benini, Luca. In Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, pp. 1–4. 2014.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{sadjun_14, author = {Sadri, MohammadSadegh and Jung, Matthias and Weis, Christian and Wehn, Norbert and Benini, Luca}, booktitle = {Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014}, keywords = {AGWehn}, month = {03}, pages = {1-4}, title = {{E}nergy {O}ptimization in 3{D} {MPS}o{C}s with {W}ide-{I}/{O} {DRAM} {U}sing {T}emperature {V}ariation {A}ware {B}ank-{W}ise {R}efresh}, year = 2014 }
• Thermal Modelling of 3D Stacked DRAM with Virtual Platforms. Jung, Matthias; Sadri, MohammadSadegh; Wehn, Norbert. In Tenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES14), Vol. 10. Academia Press, Ghent, Belgium, 2014.
  • [ BibTeX ]
  • [ URL ]
  @incollection{junsad_14, author = {Jung, Matthias and Sadri, MohammadSadegh and Wehn, Norbert}, booktitle = {Tenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES14)}, keywords = {myown}, publisher = {Academia Press, Ghent, Belgium}, title = {{T}hermal {M}odelling of 3{D} {S}tacked {DRAM} with {V}irtual {P}latforms}, volume = 10, year = 2014 }
• Optimized active and power-down mode refresh control in 3D-DRAMs. Jung, Matthias; Weis, Christian; Wehn, Norbert; Sadri, MohammadSadegh; Benini, Luca. In Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on, pp. 1–6. 2014.
  • [ BibTeX ]
  • [ DOI ]
  @inproceedings{junwei_14, author = {Jung, Matthias and Weis, Christian and Wehn, Norbert and Sadri, MohammadSadegh and Benini, Luca}, booktitle = {Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on}, keywords = {DRAM}, month = 10, pages = {1-6}, title = {{O}ptimized active and power-down mode refresh control in 3{D}-{DRAM}s}, year = 2014 }

• Power Modelling of 3D-Stacked Memories with TLM2.0 based Virtual Platforms. Jung, Matthias; Weis, Christian; Bertram, Patrick; Wehn, Norbert. In Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany. 2013.
  • [ BibTeX ]
  • [ URL ]
  @inproceedings{junwei_13a, author = {Jung, Matthias and Weis, Christian and Bertram, Patrick and Wehn, Norbert}, booktitle = {Synopsys User Group Conference (SNUG), May, 2013, Munich, Germany.}, keywords = {myown}, title = {{P}ower {M}odelling of 3{D}-{S}tacked {M}emories with {TLM}2.0 based {V}irtual {P}latforms}, year = 2013 }
• Virtual Platforms for Fast Memory Subsystem Exploration Using gem5 and TLM2.0. Jung, Matthias; Sadri, MohammadSadegh; Wehn, Norbert. In Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13), Vol. 9, pp. 153–156. Academia Press, Ghent, Belgium, 2013.
  • [ BibTeX ]
  • [ URL ]
  @incollection{junsad_13, author = {Jung, Matthias and Sadri, MohammadSadegh and Wehn, Norbert}, booktitle = {Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13)}, keywords = {myown}, pages = {153–156}, publisher = {Academia Press, Ghent, Belgium}, title = {{V}irtual {P}latforms for {F}ast {M}emory {S}ubsystem {E}xploration {U}sing gem5 and {TLM}2.0}, volume = 9, year = 2013 }
• TLM modelling of 3D stacked wide I/O DRAM subsystems: a virtual platform for memory controller design space exploration. Jung, Matthias; Weis, Christian; Wehn, Norbert; Chandrasekar, Karthik. In Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, of RAPIDO ’13, pp. 5:1–5:6. ACM, Berlin, Germany, 2013.
  • [ BibTeX ]
  • [ URL ]
  • [ DOI ]
  @inproceedings{junwei_13, address = {New York, NY, USA}, author = {Jung, Matthias and Weis, Christian and Wehn, Norbert and Chandrasekar, Karthik}, booktitle = {Proceedings of the 2013 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools}, keywords = {AGWehn}, pages = {5:1–5:6}, publisher = {ACM}, series = {RAPIDO '13}, title = {{TLM} modelling of 3{D} stacked wide {I}/{O} {DRAM} subsystems: a virtual platform for memory controller design space exploration}, year = 2013 }
• Virtual Platforms for Fast Exploration of Computing Systems in Finance. Brugger, Christian; Jung, Matthias; Omland, Steffen. In Young Researcher Symposium, YRS 2013. Proceedings, pp. 18–23. Fraunhofer Verlag, 2013.
  • [ BibTeX ]
  • [ URL ]
  @inproceedings{brujun_13, author = {Brugger, Christian and Jung, Matthias and Omland, Steffen}, booktitle = {Young Researcher Symposium, YRS 2013. Proceedings}, keywords = {myown}, month = 11, note = {ISBN 978-3-8396-0628-5, \url{http://publica.fraunhofer.de/documents/N-266783.html}}, pages = {18–23}, publisher = {Fraunhofer Verlag}, title = {{V}irtual {P}latforms for {F}ast {E}xploration of {C}omputing {S}ystems in {F}inance}, year = 2013 }

• A Scalable Multi-Core ASIP Virtual Platform For Standard-Compliant Trellis Decoding. Jung, Matthias; Brehm, Christian; Wehn, Norbert. In Synopsys User Group Conference (SNUG). Munich, Germany, 2012.
  • [ BibTeX ]
  • [ URL ]
  @inproceedings{junbre_12, address = {Munich, Germany}, author = {Jung, Matthias and Brehm, Christian and Wehn, Norbert}, booktitle = {Synopsys User Group Conference (SNUG)}, keywords = {AGWehn}, month = {05}, title = {{A} {S}calable {M}ulti-{C}ore {ASIP} {V}irtual {P}latform {F}or {S}tandard-{C}ompliant {T}rellis {D}ecoding}, year = 2012 }

• Energy Efficient Acceleration and Evaluation of Financial Computations towards Real-Time Pricing. de Schryver, Christian; Jung, Matthias; Wehn, Norbert; Marxen, Henning; Kostiuk, Anton; Korn, Ralf. In Knowledge-Based and Intelligent Information and Engineering Systems, Vol. 6884, A. König, A. Dengel, K. Hinkelmann, K. Kise, R. J. Howlett, L. C. Jain (eds.), pp. 177–186. Springer Berlin Heidelberg, Heidelberg, 2011.
  • [ BibTeX ]
  • [ URL ]
  • [ DOI ]
  @incollection{schjun_11, abstract = {Modern financial markets are as vivid as never before. Asset prices - and therefore the prices of all related financial products - change within several milliseconds nowadays. However, not only due to the financial crisis in 2008, calculating fair and meaningful prices for these products is much more important than in the past. In order to obtain reliable prices, sophisticated simulation models have to be used. Pricing in these models in general has a very high computational complexity and can in many cases only be approximately done by using numerical methods. On the other hand, we all know that energy costs will become more and more significant in the future. The gap between the increasing computational complexity and the consumed energy can only be bridged by using more tailored computation engines, like dedicated hardware accelerators or application specific instruction set processors (ASIPs). In this paper we present a comprehensive methodology for the efficient design of optimal hardware accelerators and the evaluation thereof. We give two case studies: a new hardware random number generator for arbitrary distributions and a dedicated hardware accelerator for calculating European barrier option prices.}, author = {de Schryver, Christian and Jung, Matthias and Wehn, Norbert and Marxen, Henning and Kostiuk, Anton and Korn, Ralf}, booktitle = {Knowledge-Based and Intelligent Information and Engineering Systems}, editor = {König, Andreas and Dengel, Andreas and Hinkelmann, Knut and Kise, Koichi and Howlett, Robert J. and Jain, Lakhmi C.}, keywords = {finance}, month = {09}, note = {Proceedings of 15th International Conference on Knowledge-Based and Intelligent Information \& Engineering Systems (KES)}, pages = {177–186}, publisher = {Springer Berlin Heidelberg}, series = {Lecture Notes in Computer Science}, title = {{E}nergy {E}fficient {A}cceleration and {E}valuation of {F}inancial {C}omputations towards {R}eal-{T}ime {P}ricing}, volume = 6884, year = 2011 }