Research

This project focuses on developing an open-source framework for efficient design space exploration (DSE) of DRAM memory systems, building on the existing DRAMSys simulator. As data-driven applications, such as AI, continue to grow, DRAM plays a critical role in handling vast amounts of data, with memory energy consumption becoming a significant concern. DRAMSys, developed by JMU, RPTU, and Fraunhofer IESE, offers high-speed, cycle-accurate simulations for various DRAM types (e.g., DDR5, LPDDR5, HBM3), making it a valuable tool for optimizing memory systems in SoC architectures. The project aims to automate DSE for DRAM configurations, using Pareto optimization to explore the design space and optimize parameters like bandwidth, latency, and energy consumption. DRAMSys will be extended to support emerging technologies such as Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), and next-generation DRAM standards (DDR6, HBM4, GDDR7, LPDDR6). Additionally, DRAMPower’s power modeling will be improved, and DRAMSys will be further integrated with the gem5 processor simulator. The results will be released as open-source under the BSD3 license, ensuring continued support and development beyond the project’s completion.