Completed Theses
Effects of Overclocking Profiles on the Performance of DRAM
Type:
Bachelor Thesis
Student:
Gerner Marcus
Date:
11th of April 2025
Summary:
DRAM is widely used in our technological world. There are different generations and variations of DRAM like DDR4 or DDR5. And in every generation or variation there are different manufacturers of DRAM devices like Samsung or Hynix, which build these devices in different steppings like A-Die or M-Die by Hynix for DDR5. Every of these devices have different capabilities in enhancing the performance relevant data rate and timings. To look for specialized overclockable DRAM devices can give the possibility to increase the performance by far because a lot of minimum required JEDEC specified timings can be enhanced depending on the used DRAM devices. Two of these devices, one for DDR4 and one for DDR5, are used for this thesis to overclock the timings and data rate. It delivers results up to 46 % higher performance for DDR4, respectively up to 37 % more performance for DDR5. Furthermore, two real-world environments, the AM4 as well as the AM5 platform, are compared with the DRAM simulator DRAMSys4.0 to show differences and equality between them.
Development of a GPS-DO for a Satellite Ground-Station
Type:
Bachelor Thesis
Student:
Moritz Gellermann
Date:
28th of February 2025
Summary:
In this thesis a Global Positioning System (GPS) based frequency standard is developed and build. The comparison with a commercial frequency standard shows a sufficient accuracy for the intended use in an amateur radio ground-station.
Extension of a RISC-V Core for Discrete Event Simulation Acceleration
Type:
Bachelor Thesis
Student:
Timo Grundheber
Date:
17th of November 2024
Summary:
This thesis explores integrating a hardware accelerator into a Discrete Event Simulation (DES) framework, focusing on its impact on simulation performance. A custom project using the PicoRV32 processor was developed, including a discrete event simulator in C++ and an accelerator with priority and process queues. The results showed a 1.3-2.3x speedup in execution time, particularly benefiting event-dominated simulations, highlighting the importance of hardware accelerators in modern System on Chip designs and DES.
Measuring End-to-End Latency in Applications with an FPGA
Type:
Bachelor Thesis
Student:
Yannik Stamm
Date:
20th of October 2024
Summary:
This thesis is concerned with the development of a prototype for external and online latency measurement. The concept builds upon the use of an FPGA board and measures end-to-end latency by sniffing input signals directly from input devices, encoding the inputs into the video signal, and reading the encoded inputs again. This concept is implemented with the "Snickerdoodle Black" and the "piSmasher" boards and a mouse as input device. The prototype does work with further potential being promising.
Development of an Automated Recognition of QSL Cards
Type:
Bachelor Thesis
Student:
Fabian Schmitt
Date:
6th of September 2024
Summary:
Amateur radio enables radio conversations between radio amateurs worldwide, who traditionally confirm each other with QSL cards. These cards contain the sender's and recipient's call signs and are distributed by national associations. In Germany, a sorting machine with manual assistance is used. This work aimed at improving the system with Optical Character Recognition (OCR) to automatically recognize call signs and increase the efficiency of card distribution was achieved through an improved OCR system and preprocessing.
